1. Field of the Invention
The present invention is in the field of computers and more specifically relates to a microprogram sequencer for determining the sequence of microinstructions that are used to execute a microprocessor machine instruction.
2. The Prior Art
In a microprogrammed computer, each machine instruction is implemented by a sequence of microinstructions which are stored within the microcomputer in a microprogram memory.
The sequence of microinstructions corresponding to a particular machine instruction operates the various parts of the central processing unit of the microcomputer in a particular sequence to execute the machine instruction.
Typically, in some microcomputers the operations of the various parts are controlled by enabling signals. The state of the microcomputer is uniquely specified by the set of enabling signals. During any specific clock interval, the values (levels) of the enabling signals are constant and are determined by the microinstruction being executed during that clock interval. Each microinstruction determines the states of all the enabling signals during a brief time interval.
Typically, each microinstruction is embodied in the microprocessor as an ordered set of binary digits. The microinstructions are typically stored in a ROM in the control unit of the microprocessor. Each of the binary digits may be used as one of the enabling signals during the interval over which the microinstruction is effective. Alternatively, the binary digits of a microinstruction may be decoded to obtain the values of the enabling signals.
In a typical microprocessor, a portion of the machine instruction is used to address a mapping PROM in which is stored the starting address of the microinstruction sequence that implements the machine instruction. This starting address is applied to the microprogram PROM to obtain the first microinstruction. A microsequencer is provided which in succession generates the addresses of the succeeding microinstructions by periodically incrementing a counter, the count of which is the address. These successive addresses are applied to the microprogram PROM to access the succeeding microinstructions making up the machine address.
While this method of sequencing the microinstructions is known to be feasible for some types of microprocessors, it is not as efficient as the system of the present invention, which does not require the use of a microsequencer counter.
It is known in the art to include provision for the microprogram to jump out of sequence when certain conditions are met. This is accomplished by providing in each microinstruction a field for an alternate next microinstruction address which is invoked when some certain condition obtains.
As implemented in prior art systems, this technique typically requires two clock periods to execute. During the first clock period, the conditional branching instruction is executed and upon recognition of the branching condition, the address of the alternative microinstruction is determined. During the next clock period, the microsequencer counter is loaded to the address of the alternative microinstruction, and then in the third clock period the alternative microinstruction is executed.
As will be discussed below, the present invention can handle conditional branch instructions more efficiently so that a clock period is saved each time a conditional branch instruction is executed.